Test Preparation on UGC NET Computer Science Paper-III (December 2015)

The three outputs x1x2x3 from the 8x3 priority encoder are used to provide a vector address of form 101x1x2x300. What is the second-highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority?

What will be the output at PORT1 if the following program is executed?
VMI B, 82H
MOV A, B
MOV C, A
VMI D, 37H
OUT PORT1
HELP

137H
282H
3B9H
400H

In 8085 programming, the result of an operation is stored in the accumulator. So the output is 82H.

Which of the following 8085 microprocessor hardware interrupt has the
lowest priority?

1RST 6.5
2RST 7.5
3TRAP
4INTR

A dynamic RAM has a refresh cycle of 32 times per msec. Each refresh operation requires 100 sec and a memory cycle requires 250 sec. What percentage of memory’s total operating time is required for refreshes?

10.64
20.96
32.00
40.32

in 1ms : refresh = 32 times

Memory cycle = 1ms/250ns = 106ns/250ns = 4000 times
Therefore, % of refresh time = (32 x 100ns)/(4000 x 250ns)
= 3200ns/1000000 x 100% = 0.32%
OR
TIME REQUIRED TO REFRESH 32 IN I MS IS 32 x 100ns =3200NS
percentage of memory’s total operating time is required for refreshes = =3200ns/1000000 x 100% = 0.32%

A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?

10.06%
20.12%
31.2%
42.5%

The DMA combines one word from four consecutive characters (bytes) so we get 4800 chars/s = 4800 bytes/s = 1200 words/s (one word = 32 bits = 4 bytes)

If we assume that one CPU instruction is one word wide then 1 million instructions/s = 1 million words/s = 106 word/s

So we have 1200 words received during one second and (106-1200) words processed by the CPU (while DMA is transferring a word, the CPU cannot fetch the instruction so we have to subtract the number of words transferred by DMA). While DMA transfer CPU executes only 106 - 1200 = 998800 instructions [998800 / 106] * 100 = 99.88 % Slowdown = 100 - 99.88 = 0.12%

The CPU will be slowed down by 0.12%.

A CPU handles interrupt by executing interrupt service subroutine.................

1by checking interrupt register after execution of each instruction
2by checking interrupt register at the end of the fetch cycle
3whenever an interrupt is registered
4by checking interrupt register at regular time interval

Given the following set of prolog clauses:
father(X, Y):
parent(X, Y),
male(X),
parent(Sally, Bob),
parent(Jim, Bob),
parent(Alice, Jane),
parent(Thomas, Jane),
male(Bob),
male(Jim),
female(Salley),
female(Alice).
How many atoms are matched to the variable ‘X’ before the query
father(X, Jane) reports a Result?

Forward chaining systems are ............. where as backward chaining systems are ................

1Data driven, Data driven
2Goal driven, Data driven
3Data driven, Goal driven
4Goal driven, Goal driven

In forward chaining, the data determines which rules are selected and used, this method is called data-driven.In backward chaining,e the list of goals determines which rules are selected and used, this method is called goal-driven.So correct option is (C).


Right Ans	Wrong Ans	Not Attempted